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rev.1.0, feb.25.2004, page 1 of 29 hd49335f/hf cds/pga & 10-bit a/d tg converter rej03f0100-0100z rev.1.0 feb.25.2004 description the hd49335f/hf is a cmos ic that provides cds-pga analog processing (cds/pga) suitable for ccd camera digital signal processing systems together with a 10-bit a/d converter and timing generator in a single chip. there are address map and timing generator charts besides this specification. may be contacted to our sales department if examining the details. functions ? correlated double sampling ? pga ? serial interface control ? 10-bit adc ? timing generator ? operates using only the 3 v voltage ? corresponds to switching mode of power dissipation and operating frequency power dissipation: 220 mw (typ), maximum frequency: 36 mhz (hd49335hf) power dissipation: 150 mw (typ), maximum frequency: 25 mhz (hd49335f) ? adc direct input mode ? qfp 64-pin package features ? suppresses low-frequency noise, which output from ccd by the correlated double sampling. ? the s/h response frequency characteristics for the reference level can be adjusted using values of external parts and registers. ? high sensitivity is achieved due to the high s/n ratio and a wide dynamic range provided by a pg amplifier. ? pga, pulse timing, standby mode, etc., is achieved via a serial interface. ? high precision is provided by a 10-bit-resolution a/d converter. ? difference encoded gray code can be selected as an a/d outp ut code. it is effective in suppression of solarization (wave pattern). it is patented by renesas. ? timing generator generates the all of pulse which are needed for ccd driving.
hd49335f/hf rev.1.0, feb.25.2004, page 2 of 29 pin arrangement 48 47 39 46 45 44 43 42 41 40 38 36 35 34 37 12 10 3 4 5 6 7 8 9 11 12 13 14 15 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 (top view) av dd blkc cds_in av dd blkfb blksh av ss test2 test1 dll_c dv dd 1 mon 41cont cs sdata sck xv3 xv2 xv1 dv dd 3 dv dd 4 1/4clk_o h2a dv ss 4 dv ss 4 1/2clk_o h1a dv dd 4 dv dd 3 rg reset vd_in vrm vrt vrb bias adc_in av ss dv ss 3 strob sub_pd sub_sw xsub ch4 ch3 ch2 ch1 xv4 id dv ss 1,2 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 dv dd 2 dv ss 3 clk_in hd_in 33 16 pin description pin no. symbol description i/o analog(a) or digital(d) remarks 1 id odd/even number line detecting pulse output pin o d 2 ma/10 pf 2 dv ss 1,2 cds digital ground + adc output buffer ground (0 v) ? d 3 to 12 d0 to d9 digital output (d0; lsb, d9; msb) o d 2 ma/10 pf 13 dv dd 2 adc output buffer power supply (3 v) ? d 14 dv ss 3 general ground for tg (0 v) ? d 15 clk_in clk input (max 72 mhz) i d 16 hd_in hd input i/o d 17 vd_in vd input i/o d 18 reset hardware reset (for dll reset) i d schmitt trigger 19 rg reset gate pulse output o d 3 ma/10 pf 20 dv dd 3 general power supply for tg (3 v) ? d 21 dv dd 4 h1 buffer power supply (3 v) ? d 22 h1a h.ccd transfer pulse output-1a o d 30 ma/165 pf 23 1/2clk_o clk_in 2 divided output. 3 divided output at 3 divided mode o d 2 ma/10 pf 24 dv ss 4 h1 buffer ground (0 v) ? d 25 dv ss 4 h1 buffer ground (0 v) ? d 26 h2a h.ccd transfer pulse output-2a o d 30 ma/165 pf 27 1/4clk_o clk_in 4 divided output. 6 divided output at 3 divided mode o d 2 ma/10 pf 28 dv dd 4 h2 buffer power supply (3 v) ? d 29 dv dd 3 general power supply for tg (3 v) ? d
hd49335f/hf rev.1.0, feb.25.2004, page 3 of 29 pin description (cont.) pin no. symbol description i/o analog(a) or digital(d) remarks 30 xv1 v.ccd transfer pulse output-1 o d 2 ma/10 pf 31 xv2 v.ccd transfer pulse output-2 o d 2 ma/10 pf 32 xv3 v.ccd transfer pulse output-3 o d 2 ma/10 pf 33 xv4 v.ccd transfer pulse output-4 o d 2 ma/10 pf 34 ch1 read out pulse output-1 o d 2 ma/10 pf 35 ch2 read out pulse output-2 o d 2 ma/10 pf 36 ch3 read out pulse output-3 o d 2 ma/10 pf 37 ch4 read out pulse output-4/xv6 at stripe mode o d 2 ma/10 pf 38 xsub pulse output for electronic shutter o d 2 ma/10 pf 39 sub_sw sub voltage control output-1. adck input i/o d 2 ma/10 pf 40 sub_pd sub voltage control output-2/ xv5 at stripe mode o d 2 ma/10 pf 41 strob flash control output. input vgate at hi of pin 61 i/o d 2 ma/10 pf 42 dv ss 3 general ground for tg (0 v) ? d 43 av ss analog ground (0 v) ? a 44 adc_in ad converter input pin i a 45 bias bias standard resistance ? a 46 vrb adc bottom standard voltage (0.1 f for gnd) ? a 47 vrt adc top standard voltage (0.1 f for gnd) ? a 48 vrm adc middle standard voltage (0.1 f for gnd) ? a 49 av dd analog power supply (3 v) ? a 50 blkc black level c pin (1000 pf for gnd) ? a 51 cds_in cds input pin i a 52 av dd analog power supply (3 v) ? a 53 blkfb black level fb pin (1 f between blkfb and blksh) i a 54 blksh black level s/h pin o a 55 av ss analog ground (0 v) ? a 56 test2 h: normal operation, l: cds single operation mode input 36; pblk at testing, input 37; obp, input 38; cpdm, input 39; adck, input 40; sp2, input 41; sp1 i d 57 test1 l: slave mode, h: master mode i d 58 dll_c analog delay dll external c pin (100 pf for gnd) o a 59 dv dd 1 digital power supply (3 v) cds, pag, adc part ? d 60 mon pulse monitor (sp1, sp2, adck, obp, cpdm, pblk input) o d 2 ma/10 pf 61 41cont input strob = pin 41, input sub_sw = pin 39 at low input vgate = pin 41, input adck = pin 39 at hi i d 62 cs serial data cs at cds part i d 63 sdata input serial data i d 64 sck input serial clock i d
hd49335f/hf rev.1.0, feb.25.2004, page 4 of 29 input/output equivalent circuit pin name equivalent circuit d0 to d9, hd_in, vd_in, h1a, h2a, 1/2clk_o, 1/4clk_o, 41cont, sub_sw, sub_pd din dv dd enable digital output digital output id, rg, mon, xv1 to xv4, ch1 to ch4, xsub din dv dd digital output digital input clk_in, hd_in, vd_in, adclk, obp, spblk, spsig, cs, sck, sdata, pblk, oeb, reset, test1, test2, sub_sw, strob *1 digital input dv dd note: only oeb is pulled down to about 70 k ? . cds_in cds_in av dd internally connected to vrt adc_in a dc_in av dd internally connected to vrt blksh, blkfb, blkc blkfb av dd blksh blkc ? + vrt, vrm, vrb ? + ? + vrt vrm vrb av dd ? + analog bias bias av dd
hd49335f/hf rev.1.0, feb.25.2004, page 5 of 29 block diagram 10bit adc av ss vrb vrm vrt cds_in cds blksh blkc adc_in sub_sw sub_pd strob d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reset dv ss 1 to 4 blkfb cs sdata sck dll_c mon id bias timing generator vd_in hd_in clk_in xsub ch4 ch3 ch2 ch1 xv4 xv3 pblk cpdm obp adclk sp2 sp1 xv2 xv1 1/4clk_o h2a 1/2clk_o h1a rg av dd dv dd 1 to 4 pga dll output latch circuit dc offset compensation circuit serial interface bias generator
hd49335f/hf rev.1.0, feb.25.2004, page 6 of 29 internal functions functional description ? cds input ? ccd low-frequency noise is suppressed by cds (correlated double sampling). ? the signal level is clamped at 14 lsb to 76 lsb by resister during the ob period. * 1 ? gain can be adjusted using 8 bits of register (0.132 db steps) within the range from ?2.36 db to 31.40 db. * 2 ? adc input ? the center level of the input signal is clamped at 512 lsb (typ). ? gain can be adjusted using 8 bits of register (0.01784 times steps, register settings) within the range from 0.57 times (?4.86 db) to 5.14 times (14.22 db). * 2 ? automatic offset calibration of pga and adc ? dc offset compensation feedback for ccd and cds ? pre-blanking ? digital output is fixed at clamp level ? digital outputs enable function note: 1. it is not covered by warranty when 14lsb settings 2. full-scale digital output is defined as 0 db (one time) when 1 v is input. operating description figure 1 shows cds/pga + adc function block. dac c3 cds amp pg amp cds_in blkfb blksh sh amp c2 c1 vrt sp1 sp1 sp2 10bit adc d0 to d9 blkc c4 obp adc_in offset calibration logic dc offset feedback logic gain setting (register) clamp data (register) current dac figure 1 cds/pga functional block diagram 1. cds (correlated double sampling) circuit the cds circuit extracts the voltage differential between th e black level and a signal including the black level. the black level is directly sampled at c1 by using the sp1 pulse, buffered by the shamp, then provided to the cdsamp. the signal level is directly sampled at c2 by using the sp2 pulse, and then provided to cdsamp (see figure 1). the difference between these two signal levels is extracted by the cdsamp, which also operates as a programmable gain amplifier at the previous stage. the cds input is biased with vrt (2 v). during the pblk period, the above sampling and bias operation are paused. 2. pga circuit the pgamp is the programmable gain amplifier for the latter stage. the pgamp and the cdsamp set the gain using 8 bits of register. the equation below shows how the gain changes when register value n is from 0 to 255. in cdsin mode: gain = (?2.36 db + 0.033 db) n (log linear). in adcin mode: gain = (0.57 times + 0.001784 times) n (linear). full-scale digital output is defined as 0 db (one time) when 1 v is input.
hd49335f/hf rev.1.0, feb.25.2004, page 7 of 29 3. automatic offset calibration function and black-level clamp data settings the dac dc voltage added to the output of the pga amplifier is adjusted by automatic offset calibration. the data, which cancels the output offset of the pga amplifier and the input offset of the adc, and the clamp data (14 lsb to 76 lsb) set by register are added and input to the dac. the automatic offset calibration starts automatically after the reset mode set by register is cancelled and terminates after 40000 clock cycles (when fclk = 20 mhz, 2 ms). 4. dc offset compensation feedback function feedback is done to set the black signal level input during the ob period to the dc standard, and all offsets (including the ccd offset and the cdsamp offset) are compensated for. the offset from the adc output is calculated during the ob period, and shamp feedback capacitor c3 is charged by the current dac (see figure 1). the open-loop differential gain ( ? gain/ ? h) per 1 h of the feedback loop is given by the following equation. 1h is the one cycle of the obp. ? gain/ ? h = 0.078/(fclk c3) (fclk: adclk frequency, c3: shamp external feedback capacitor) example: when fclk = 20 mhz and c3 = 1.0 f, ? gain/ ? h = 0.0039 when the pgamp gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop gain is increased by a multiple of n. loop gain multiplication factor n can be selected from 2 times, 4 times, 8 times, or 16 times by changing the register settings (see table 1). note that the open-loop differential gain ( ? gain/ ? h) must be one or lower. if it is two or more, oscillation occurs. the time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be selected from 1 h, 2 h, 4 h, or 8 h. if the offset error is over 16 lsb, the high-speed lead-in operation continues, and when the offset error is 16 lsb or less, the operation returns to the normal loop-gain operation after 1 h, 2 h, 4 h, or 8 h depending on the register settings. (refer to table 2.) table 1 loop gain multiplication factor during high-speed lead-in operation table 2 high-speed lead-in operation cancellation time hgain-nsel (register settings) multiplication factor n hgstop-hsel (register settings) cancellation time [0] l h l h [1] l h h l 4 32 16 8 [0] l h l h [1] l h h l 1 h 8 h 4 h 2 h 5. pre-blanking function during the pblk input period, the csd input operation is separated and protected from the large input signal. the adc digital output is fixed to clamp data (14 to 76 lsb).
hd49335f/hf rev.1.0, feb.25.2004, page 8 of 29 6. adc digital output control function the adc digital output includes the functions output enable, code conversion, and test mode. tables 3, 4 and 5 show the output functions and the codes. table 3 adc digital output functions h l h l l l h h h h l l l l h h h h l l l l h h h h l l l l h h h h l l l l h h x l l l l h l l l l h x x x x x l h l h x l h l h x l h l h x l l h h x l l h h x l l h h x l h x x l h h l stby d9 test0 d0 d1 d2 d3 d4 d5 d6 d7 d8 pblk minv test1 linv hi-z same as in table 4. d9 is inverted in table 4. d8 to d0 are inverted in table 4. d9 to d0 are inverted in table 4. output code is set up to clamp level. same as in table 5. d9 is inverted in table 5. d8 to d0 are inverted in table 5. d9 to d0 are inverted in table 5. output code is set up to clamp level. low-power wait state normal operation pre-blanking normal operation pre-blanking test mode operating mode adc digital output note: 1. stby, test, linv, and minv are set by register. table 4 adc output code (binary) d1 h l l h h l l l h h d0 h l h l h l l h l h d2 l h h h h l h h h h d7 l l l l h l h h h h d5 l l l l h l h h h h d4 l l l l h l h h h h d3 l l l l h l h h h h d6 l l l l h l h h h h d8 l l l l h l h h h h d9 l l l l l h h h h h 3 4 5 6 511 512 1020 1021 1022 1023 output pin output codes steps table 5 adc output code (gray) d8 l l l l h h l l l l d9 l l l l l h h h h h 3 4 5 6 511 512 1020 1021 1022 1023 d1 h h h l l l h h l l d0 l l h h l l l h h l d2 l h h h l l l l l l d7 l l l l l l l l l l d5 l l l l l l l l l l d4 l l l l l l l l l l d3 l l l l l l l l l l d6 l l l l l l l l l l output pin output codes steps
hd49335f/hf rev.1.0, feb.25.2004, page 9 of 29 7. adjustment of black-level s/h response frequency characteristics the cr time constant that is used for sampling/hold (s/h) at the black level can be adjusted by changing the register settings, as shown in table 6. table 6 shsw cr time constant setting 31 blkc c recommendation value of c is 1000 pf the shamp frequency characteristics can be adjusted by changing the register settings and the c4 value of the external pin. the settings are shown in table 7. values other than those shown in the table 7 cannot be used. 8. 2.20 nsec (72 mhz) 2.30 nsec (69 mhz) 2.51 nsec (63 mhz) 2.64 nsec (60 mhz) 2.93 nsec (54 mhz) 3.11 nsec (51 mhz) 3.52 nsec (45 mhz) 3.77 nsec (42 mhz) l [3] l [0] l [0] 4.40 nsec (36 mhz) 4.80 nsec (33 mhz) l [1] l [1] l [2] l [2] 5.87 nsec (27 mhz) 6.60 nsec (24 mhz) 8.80 nsec (18 mhz) 10.6 nsec (15 mhz) 17.6 nsec (9 mhz) 26.4 nsec (6 mhz) l [3] h [3] h [0] h [0] l [1] l [1] l [2] l [2] l [3] h [3] l [0] l [0] h [1] h [1] l [2] l [2] l [3] h [3] h [0] h [0] h [1] h [1] l [2] l [2] l [3] h [3] l [0] l [0] l [1] l [1] h [2] h [2] l [3] h [3] h [0] h [0] l [1] l [1] h [2] h [2] l [3] h [3] l [0] l [0] h [1] h [1] h [2] h [2] l [3] h [3] h [0] h [0] h [1] h [1] h [2] h [2] h [3] shsw-fsel (register setting) shsw-fsel (register setting) cr time constant (typ) (cutoff frequency conversion) cr time constant (typ) (cutoff frequency conversion) table 7 shamp frequency characteristics setting 230 mhz 6800 pf (240 pf) 56 mhz 18000 pf (360 pf) 116 mhz 10000 pf (270 pf) 100 mhz 10000 pf (560 pf) "lo" "hi" 24 mhz 27000 pf (820 pf) 75 mhz 13000 pf (300 pf) 32 mhz 22000 pf (750 pf) 49 mhz 15000 pf (620 pf) l [0] h [0] l [1] l [1] l [0] h [1] h [0] h [1] sha-fsel (register setting) lopwr (register setting) note: upper line middle line lower line : shamp cutoff frequency (typ) : standard value of c4 (maximum value is not defined) : minimum value of c4 (do not set below this value)
hd49335f/hf rev.1.0, feb.25.2004, page 10 of 29 timing chart figure 2 shows the timing chart when cdsin and adcin input modes are used. 012 910 11 n+1 n+2 n+9 n+10 n+11 n cds_in sp1 sp2 adclk d0 to d9 n+2 n+8 n+9 n+10 n+11 n ? 8 n ? 9n ? 1 adc_in adclk d0 to d9 n n+1 n n+1 n ? 9n ? 8n ? 1 n n ? 10 ? when cds_in input mode is used ? when adc_in input mode is used ~ figure 2 output timing chart when cdsin and adcin input modes are used ? the adc output (d0 to d9) is output at the rising edge of the adclk in both modes. ? pipe-line delay is ten clock cycles when cdsin is used and nine when adcin is used. ? in adcin input mode, the input signal is sampled at the rising edge of the adclk.
hd49335f/hf rev.1.0, feb.25.2004, page 11 of 29 detailed timing specifications detailed timing specifications wh en cdsin input mode is used figure 3 shows the detailed timing specifications when the cdsin input mode is used, and table 8 shows each timing specification. cds_in sp1 vth (2) (3) sp2 a dclk (7) vth vth (8) (9) (10) (4) (1) (5) (11) (6) (13) (12) d0 to d9 h1 black level signal level figure 3 detailed timing chart when cdsin input mode is used table 8 timing specifications when the cdsin input mode is used no. timing symbol min typ max unit (1) black-level signal fetch time t cds1 ? (1.5) ? ns (2) sp1 ?hi? period t cds2 typ 0.8 1/4f clk typ 1.2 ns (3) signal-level fetch time t cds3 ? (1.5) ? ns (4) sp2 ?hi? period t cds4 typ 0.8 1/4f clk typ 1.2 ns (5) sp1 falling to sp2 falling time t cds5 typ 0.85 1/2f clk typ 1.15 ns (6) sp1 falling to adclk rising inhibit time t cds6 ? (5) ? ns (7), (8) adclk t wh min./t wl min t cds7, 8 11 ? ? ns (9) adclk rising to digital output holding time t chld9 ? (7) ? ns (10) adclk rising to digital output delay time t cod10 ? (16) ? ns (11) h1 rising to adclk rising time t cds11 ? (1/4f clk ) ? ns (12) h1 rising to spsig falling time t cds12 ? (1/f clk ) ? ns (13) h1 rising to spblk falling time t cds13 ? (1/2f clk ) ? ns obp detailed timing specifications figure 4 shows the obp detailed timing specifications. the ob period is from the fifth to the twelfth clock cycle after the ob pulse is inputted. the average of the black signal level is taken for eight input cycles during the ob period and it becomes the clamp level (dc standard). cds_in obp n n+1 n+5 n+12 n+13 note: ob pulse > 2 clock cycles ob period * 1 1. shifts 1 clock cycle depending on the obp input timing. figure 4 obp detailed timing specifications
hd49335f/hf rev.1.0, feb.25.2004, page 12 of 29 detailed timing specifica tions at pre-blanking figure 5 shows the pre-blanking detailed timing specifications. digital output (d0 to d9) adc data clamp level adc data pblk adclk 2 clock adclk 10 clock vth v ol v oh figure 5 detailed timing sp ecifications at pre-blanking detailed timing specifications wh en adcin input mode is used figure 6 shows the detailed timing chart when adcin input mode is used, and table 9 shows each timing specification. a dc_in (1) a dclk d0 to d9 (2) vth v dd /2 (3) (5) (4) figure 6 detailed timing chart when adcin input mode is used table 9 timing specifications when adcin input mode is used no. timing symbol min typ max unit (1) signal fetch time t adc1 ? (6) ? ns (2), (3) adclk t wh min./t wl min. t adc2, 3 typ 0.85 1/2f adclk typ 1.15 ns (4) adclk rising to digital output hold time t ahld4 ? (14.5) ? ns (5) adclk rising to digital output delay time t aod5 ? (23.5) ? ns
hd49335f/hf rev.1.0, feb.25.2004, page 13 of 29 dummy clamp it adjusts the mis-clamp which occurs when taking the phot o under the highlight conditions. (like a sun) normally it woks with the ob clamp, however when black level is out of the range caused by hightlight enter to ob part, it changes to clamp processing by dummy bit level. resister settings are follows. d12, d11, d10 of address h'f7 (dummy cp) 0, 0, 0 ; off 0, 0, 1 ; +32 0, 1, 0 ; +64 0, 1, 1 ; +96 : : 1, 1, 1 ; +224 the amount of offset are changes automatically depends on pga gain in the lsi. d8, d8 of address h'f7 (dmcg) the amount of feed back current can be reduced with only dummy clamp. data = 0:1/4 1:1/8 2:1/16 3:1/32 d10 to d12 of address h'f7 note: ob/dummy switching part has 1/8 hysteresis of threshold value. d8 to d9 of address h'f7 digital output cds agc cds_in blkfb blksh sh amp vrt sp1 sp2 sp1 on/off clamp level + ? ? + + (+) ( ? ) adc ob det current cell dummy det detect 4clk from opdm edge detect 8clk from obp edge figure 7 internal bias circuitry
hd49335f/hf rev.1.0, feb.25.2004, page 14 of 29 absolute maximum ratings (ta = 25 c) item symbol ratings unit power supply voltage v dd 4.1 v analog input voltage v in ?0.3 to av dd +0.3 v digital input voltage v i ?0.3 to dv dd +0.3 v operating temperature range ta ?20 to +85 c power dissipation pt 590 mw storage temperature tstg ?55 to +125 c power supply voltage vopr 2.70 to 3.30 v note: av dd , av ss are analog power source systems of cds, pga, and adc. dv dd 1, dv ss 1 are digital power source systems of cds, pga and adc. dv dd 2, dv ss 2 are buffer power source systems of adc output. dv dd 3, dv ss 3 are general digital power source systems of tg. dv dd 4, dv ss 4 are buffer power source systems of h1 and h2. ? pin 2 multi bonds the dv ss 1 and dv ss 2 ? when pin 64 is set to low, pin 41 = strob output, pin 39 = sub_sw output when hi, pin 41 = vgate input, pin 39 = adck input electrical characteristics (unless othewide specified, ta = 25c, av dd = 3.0 v, dv dd = 3.0 v, and r bias = 33 k ? ) ? items common to cdsin and adcin input modes item symbol min typ max unit test conditions remarks power supply voltage range v dd 2.70 3.00 3.30 v f clk hi 20 ? 36 mhz lopwr = low * 2 hd49335hf conversion frequency f clk low 5.5 ? 25 mhz lopwr = high * 2 hd49335f v ih2 dv dd 3.0 2.25 ? dv dd v digital input voltage v il2 0 ? dv dd 3.0 0.6 v cs, sck, sdata v oh dv dd ?0.5 ? ? v i oh = ?1 ma digital output voltage v ol ? ? 0.5 v i ol = +1 ma i ih ? ? 50 a v ih = 3.0 v digital input current i il ?50 ? ? a v il = 0 v adc resolution res 10 10 10 bit adc integral linearity inl ? (2) ? lsbp-p f clk = 25 mhz adc differential linearity+ dnl+ ? 0.3 0.99 lsb f clk = 25 mhz *1 adc differential linearity? dnl? ?0.99 ?0.3 ? lsb f clk = 25 mhz *1 sleep current i slp ?100 0 100 a digital input pin is set to 0 v, output pin is open standby current i stby ? 3 5 ma digital i/o pin is set to 0 v notes: 1. differential linearity is the calculated difference in linearity errors between adjacent codes. 2. 2 divided mode: f clk = 1/2clk_in 3 divided mode: f clk = 1/3clk_in 3. values within parentheses ( ) are for reference.
hd49335f/hf rev.1.0, feb.25.2004, page 15 of 29 electrical characteristics (cont.) (unless othewide specified, ta = 25c, av dd = 3.0 v, dv dd = 3.0 v, and r bias = 33 k ? ) ? items for cdsin input mode item symbol min typ max unit test conditions remarks consumption current (1) i dd1 ? 84 96.6 ma f clk = 36 mhz cdsin mode lopwr = low consumption current (2) i dd2 ? 58 66.7 ma f clk = 20 mhz cdsin mode lopwr = high ccd offset tolerance range v ccd (?100) ? (100) mv timing specifications (1) t cds1 ? (1.5) ? ns timing specifications (2) t cds2 typ 0.8 1/4f clk typ 1.2 ns timing specifications (3) t cds3 ? (1.5) ? ns timing specifications (4) t cds4 typ 0.8 1/4f clk typ 1.2 ns timing specifications (5) t cds5 typ 0.85 1/2f clk typ 1.15 ns timing specifications (6) t cds6 1 5 9 ns timing specifications (7) t cds7 ? 1/2f clk ? ns timing specifications (8) t cds8 ? 1/2f clk ? ns timing specifications (9) t chld9 ? (7) ? ns c l = 10 pf timing specifications (10) t cod10 ? (16) ? ns c l = 10 pf timing specifications (11) t cds11 ? (1/4f clk ) ? ns timing specifications (12) t cds12 ? (1/f clk ) ? ns timing specifications (13) t cds13 ? (1/2f clk ) ? ns refer to table 8 clp(00) ? (14) ? lsb clp(09) ? (32) ? lsb clamp level clp(31) ? (76) ? lsb agc(0) ?4.4 ?2.4 ?0.4 db agc(63) 4.1 6.1 8.1 db agc(127) 12.5 14.5 16.5 db agc(191) 21.0 23.0 25.0 db pga gain at cds input agc(255) 29.4 31.4 33.4 db *1 dll_2 11 ? 25 mhz *2 dll_3 7 ? 11 mhz *3 dll operation frequency dll_4 5.5 ? 7 mhz *4 t/g 3/1divided operation frequency range clk_in3 28.6 ? 28.6 mhz f clk = 1/3clk_in3 v oh 2.94 2.97 ? v 30 ma buff, i oh = ?5 ma v ol ? 22 47 mv 30 ma buff, i ol = +5 ma v oh 2.89 2.94 ? v 14 ma buff, i oh = ?5 ma v ol ? 50 112 mv 14 ma buff, i ol = +5 ma v oh 2.91 2.96 ? v 10 ma buff, i oh = ?3 ma v ol ? 36 78 mv 10 ma buff, i ol = +3 ma v oh 2.85 2.93 ? v 4 ma buff, i oh = ?2 ma v ol ? 60 129 mv 4 ma buff, i ol = +2 ma v oh 2.69 2.86 ? v 2 ma buff, i oh = ?2 ma h buffer output voltage v ol ? 115 262 mv 2 ma buff, i ol = +2 ma v oh 2.81 2.90 ? v i oh = ?2 ma rg output voltage v ol ? 78 141 mv i ol = +2 ma notes: 1. define digital output full scall with 1 v input as 0 db. 2. number of master steps: 60 steps, dll current high 3. number of master steps: 40 steps, dll current low 4. number of master steps: 60 steps, dll current low 5. values within parentheses ( ) are for reference.
hd49335f/hf rev.1.0, feb.25.2004, page 16 of 29 electrical characteristics (cont.) (unless othewide specified, ta = 25c, av dd = 3.0 v, dv dd = 3.0 v, and r bias = 33 k ? ) ? items for adcin input mode item symbol min typ max unit test conditions remarks consumption current (3) i dd3 ? 32 38.4 ma f clk = 36 mhz adcin mode lopwr = low consumption current (4) i dd4 ? 22 27.5 ma f clk = 25 mhz adcin mode lopwr = high timing specifications (14) t adc1 ? (6) ? ns timing specifications (15) t adc2 typ 0.85 1/2f adclk typ 1.15 ns timing specifications (16) t adc3 typ 0.85 1/2f adclk typ 1.15 ns timing specifications (17) t ahld4 ? (14.5) ? ns c l = 10 pf timing specifications (18) t aod5 ? (23.5) ? ns c l = 10 pf refer to table 9 input current at adc input iin cin ?110 ? 110 a v in = 1.0 to 2.0 v clamp level at adc input of2 ? (512) ? lsb gsl(0) 0.45 0.57 0.72 times gsl(63) 1.36 1.71 2.16 times gsl(127) 2.27 2.86 3.60 times gsl(191) 3.18 4.00 5.04 times pga gain at adc input gsl(255) 4.08 5.14 6.47 times note : values within parentheses ( ) are for reference.
hd49335f/hf rev.1.0, feb.25.2004, page 17 of 29 serial interfa ce specifications timing specifications sdata std2(upper data) std1(lower data) address(address) sck cs f sck d9 d8 d11 d10 d13 d12 d15 d14 d1 d0 d3 d2 d5 d4 d7 d6 d0 d2 d1 d4 d3 d6 d5 d7 t int1 t int2 t su t ho latches sdata at sck rising edge data is determined at cs rising edge figure 8 serial interf ace timing specifications item min max f sck ? 5 mhz t int1,2 50 ns ? t su 50 ns ? t ho 50 ns ? notes: 1. 3 byte continuous communications. 2. input sck with 24 clock when cs is low. 3. it becomes invalid when data communications are stopped on the way. 4. data becomes a default with hardware reset. 5. input more than double frequency of sck to the clk_in when transfer the serial data. the kind of data data address has 256 type. h?00 to h?ff h?00 : : h?ef data at timing generator part h?f0 : : h?ff data at cds part address map of each data referred to other sheet. details of timing generator refer to the timing chart on the other sheet together with this specification. this specification only explains about the data of cds part.
hd49335f/hf rev.1.0, feb.25.2004, page 18 of 29 explanation of serial data of cds part serial data of cds part are assigned to a ddress h?f0 to h?f8. functions are follows. address std1[7:0] (l) pga gain std2[15:8] (h) 1 1 1 1 0 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 test_i1 ? pga gain (d0 to d7 of address h?f0) details are referred to page 5 block diagram. at cds_in mode: ?2.36 db + 0.132 db n (log linear) at adc_in mode: 0.57 times + 0.01784 times n (times linear) ? : full-scale digital output is defined as 0 db when 1 v is input. above pga gain definition means input signal 1 vp-p to cds_in, and set n = 18 (correspond 2.36 db), and then pga outputs the 2 v full-range, and also adc out puts the full code (1023). this mean offset gain of pga has 6 db ? 2.36 db = 3.64 db, therefore it should be decided that how much db add on. (1) level dia explain cds pga 0 db when set n = 18 which correspond to 2.36 db adc (2) level dia on the circuit cds pga 3.64 db + 0.132 db n (cds = 0 db) adc 2 v 1023 (1.0 v) (1.0 v) (2.0 v) (1023) figure 9 level dia of pga ? test_i1 (d13 to d15 of address h?f0) it controls the standard current of analog amplifier systems of cds, pga. use data = 4 (d15 = 1) normally. when data = 0, 50% current value with default when data = 4, default when data = 7, 150% current value with default address std1[7:0] (l) std2[15:8] (h) 1 1 1 1 0 0 0 1 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 sha_fsel test_i2 shsw_fsel test0 minv linv stby slp ? slp and stby (d0, d1 of address h?f1) slp: stop the all circuit. consumption current of cds part is less than 10 a. start up from offset calibration when recover is needed. stby: only the standard voltage generating circuit is operated. consumption current of cds part is about 3 ma. allow 50 h time for feedback clamp is stabilized until recover.
hd49335f/hf rev.1.0, feb.25.2004, page 19 of 29 ? output mode (d2 to d4 of address h?f1 and address h?f4 of d6) it is a test mode. combination details are table 3 to 5. normally set to all 0. ? sha-fsel (d8 to d9 of address h?f1) it is a lpf switching of sh amplifier. frequency characteristics are referred to page 8. to get rough idea, set the double cut off frequency point with using. ? shsw-fsel (d10 to d13 of address h?f1) it is a time constant which sampling the black level of sh amplifier. frequency characteristics are referred to page 8. to get rough idea, set the double cut off frequency point with using. s/n changes by this data, so find the appropriate point with set data to up/down. ? test_i2 (d14 to d15 of address h?f1) current of adc analog part can be set minutely. normally use data = 0. 0: default (100%) 1: 150% 2: 50% 3: 80% address std1[7:0] (l) hgain-nsel std2[15:8] (h) 1 1 1 1 0 0 1 0 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 clamp level reset ad_sel cds_buff low_pwr hgstop-hsel ? clamp (d0 to d4 of address h?f2) determine the ob part level with digital code of adc output. clamp level = setting data 2 + 14 default data is 9 = 32 lsb. ? hgstop-hsel, hgain-nsel (d8 to d11 of address h?f2) determine the lead-in speed of ob clamp. details are referred to page 7. pga gain need to be changed for switch the high speed leading mode. transfer the gain +1/?1 to previous field, its switch to high speed leading mode. ? low_pwr (d12 of address h?f2) switch circuit current and frequency characteristic. data = 0: 36 mhz guarantee data = 1: 25 mhz guarantee ? adsel (d14 of address h?f2) data = 0: select cds_in data = 1: select adc_in ? reset (d15 of address h?f2) software reset. data = 1: normal data = 0: reset offset calibration should be done when starting up with using this bit. details are referred to page 23. address std1[7:0] (l) std2[15:8] (h) 11110011 d4d3d2 d7 d6 d5 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 ? address h'f3 are all testing data. normally set to all 0., or do not transfer the data.
hd49335f/hf rev.1.0, feb.25.2004, page 20 of 29 address std1[7:0] (l) std2[15:8] (h) 11110100 d4d3d2 d7 d6 d5 d1 d0 d12 d11 d10 d9 d8 gray_test vd latch mon gray code h12_buff ? mon (d0 to d2 of address h?f4) select the pulse which output to pin mon (pin 60). when d0 to d2: 0, fix to low when 1, adclk when 2, sp1 when 3, sp2 when 4, obp when 5, pblk when 6, cpdm when 7, dll_test ? h12baff (d3 to d6 of address h?f4) select the buffer size which output to pin h1a, h2a (pin 22, 26). d3: 2 ma buffer d4: 4 ma buffer d5: 10 ma buffer d6: 14 ma buffer above data can be on/off individually. default is d6 can be on only. (18 ma buffer) ? vd latch (d7 of address h?f4) data = 0: gain data is determined when cs rising data = 1: gain data is determined when vd falling differential code and gray code (d8 to d12 of address h?f4) ? gray code (d8 to d9 of address h?f4) dc output code can be change to following type. gray code [1] gray code [0] output code 0 0 binary code 0 1 gray code 1 0 differential encoded binary 1 1 differential encoded gray ? serial data setting items (d10 to d12 of address h?f4) setting bit setting contents gray_test[0] gray_test[1] standard data output timing control signal (refer to the following table) gray_test[2] adclk polar with obp. (lo positive edge, hi negative edge) ? standard data output timing gray_test[1] gray_test[0] sta ndard data output timing low low third and fourth low high fourth and fifth high low fifth and sixth high high sixth and seventh
hd49335f/hf rev.1.0, feb.25.2004, page 21 of 29 ripple (pseudo outline made by quantized error) occurres on the point which swithing the adc output multiple bit in parallel. when switching the several of adc output at the same time, ripple (pseudo outline caused by miss quantization) occurs to the image. differential code and gray code are recommended for this countermeasure. figure 10 indicates circuit block. when luminance signal changes are smoothly, the number of bit of switching digital output bit can be reduced and easily to reduce the ripple using this function. this function is especially effective for longer the settings of sensor more than clk = 30 khz, and adc output. figure 11 indicates the timing specifications. adc 10 differential sw(d9) carry bit round + ? gray sw(d8) standard data control signal (d12,d11,d10) standard data selector 10-bit output 2clk_dl gray binary conversion figure 10 diff erential code, gray code circuit 1 a dclk obp digital output (beginning edge of obp and standard edge of adclk should be exept 5 ns) (in case of select the positive edge of adclk with d12) (in case of select the positive polar) differential data standard data differential data 2345678910 11 figure 11 differen tial code timing specifications to use differential code, complex circuit is necessary at dsp side. (1) differential coded from adc standard data control signal carry bit round 2clk_dl standard data selector d11 d11 d10 d9 d0 d10 d9 d0 gray binary (2) gray binary conversion figure 12 complex circuit example address std1[7:0] (l) std2[15:8] (h) 11110101 d4d3d2 d7 d6 d5 d1 d0 d12 d11 d10 d9 d8 p_sp1 p_sp2 p_adclk p_rg dll steps dll current 2,3 divided select address std1[7:0] (l) std2[15:8] (h) 11111000 d4 d2 d6 d5 d1 d0 d12 d10 d15 d14 d13 d9 d8 p_sp2 p_sp1 p_adclk p_rg
hd49335f/hf rev.1.0, feb.25.2004, page 22 of 29 ? address h?f5 sets the dll delay time and selects the 1/4 phase. details are on the next page. and d15 of address h?f8 can switch 2/3 divided mode but ensure that this address data relative to valid/invalid. d15 of address h?f8 = 0 d15 of address h?f8 = 1 divided mode 2 divided, 1/4 phase select 3 divided, 1/6 phase select d0 to d7 of address h?f5 valid invalid d0 to d14 of address h?f8 invalid valid ? phase settings of high speed pulse (address h?f5 to h?f8) (1) select the 1/4 phase from figure 13 at 2 divided mode (d15 = 0 of address h?f8). select the 1/6 phase from figure 14 at 3 divided mode (d15 = 1 of address h?f8). p_sp1, p_sp2, p_adclk, p_rg (2) then select the necessary delay time from figure 15. dl_sp1, dl_sp2, dl_rg, dl_adclk rg can be set both of rising / falling edge optionally. h1 data = 0 data = 1 data = 3 data = 2 p_sp1 p_sp2 h1 data = 0 data = 1 data = 3 data = 2 p_adclk p_rg figure 13 2 divided mode, 1/4 phase select (valid at d15 = 0 of address h?f8) h1 data = 5 data = 2 data = 3 data = 4 data = 1 data = 0 p_sp1 p_sp2 h1 data = 0 data = 3 data = 4 data = 5 data = 2 data = 1 p_adclk p_rg figure 14 3 divided mode, 1/6 phase select (valid at d15 = 1 of address h?f8) default value of each phases p_sp1 p_sp2 p_adclk p_rg 2 divided mode 1 2 1 0 3 divided mode 0 3 1 5 note: 50% of duty pulse makes tr, tf of rg by dll. address std1[7:0] (l) std2[15:8] (h) 11110110 d4d3d2 d7 d6 d5 d1 d0 d12 d11 d10 d9 d8 dl_sp2 dl_sp1 dl_rg_f dl_rg_r dl_adclk cds_test address std1[7:0] (l) std2[15:8] (h) 11110111 d4d3d2 d7 d6 d5 d1 d0 d12 d11 d10 d9 d8 dummy clamp th dummy clamp current
hd49335f/hf rev.1.0, feb.25.2004, page 23 of 29 (3) setting method of dll 28 14 0 1. 2. 3. 42 ? default 56 10 h1 dll step decides the how many divide the 1 cycle of sensor clk. for reference, set 1 ns(when 2 ns dll_current bit = 0, when 1 set to 1 ns) can be set 16 to 64 steps by 4 steps. steps = 4 + (4 n); possible to set n = 3 to 15 recommended steps is clk_in = when 11 to 14 mhz: h'0e(60 steps) when 14 to 22mhz: h'09(40 steps) when 22 to 50mhz: h'1e(60 steps) when 50 to 72mhz: h'19(40 steps) can be change each 4 type of pulse 0 to 15 steps with 1 step. (1 ns or 2 ns divide) select the 2 ns divide when sensor clk is less than 15 mhz. dl_rg dl_sp1 dl_adclk dl_sp2 dl_adclk dll_c control voltage p_adclk and pc dll = 64 steps adclk(0) (in phase with h1) dll = 15 steps dl_sp1 p_sp1 dll = 15 steps dl_sp2 (falling) (rising) p_sp2 dll = 15 steps adclk (0, 0) dl_rg dll = 15 steps figure 15 analog delay (dll) circuit block. ? cds_test (d12 of address h?f6) it is testing data. normally set to 0. ? dummy clamp current (d9 to 8 of address h?f7) data = when 0, 1/4 when 1, 1/8 when 2, 1/16 when 3, 1/32 details are refer to page 12. ? dummy clamp threshold (d12 to 10 of address h?f7) data = when 0, off when 1, +32 when 2, +64 when 3, +96 when 4, +128 when 5, +160 when 6, +192 when 7, +224 details are refer to page 12.
hd49335f/hf rev.1.0, feb.25.2004, page 24 of 29 operation sequence at power on v dd (1) resistor transfer of tg part (2) dll data transfer of cds part (3) reset=l of cds part (4) reset=h of cds part (5) other data of cds part : wait more than 6clk after release the hardware reset and then transfer the necessary data to tg part. : transfer the phase data of rg, sp1, sp2, adclk of cds part. : transfer reset bit = 0 of address h'f2. : transfer reset bit = 1 of address h'f2. (reset release) : transfer the sh_sw_fsel and other pga. clk_in hardware reset 3clk or more 6clk or more (1) 2ms or more (charge of external c) 40,000adclk or more (offset calibration) (2) (3) (4) cds_reset = low (5) note: at 2 divided mode: adclk = 1/2clk_in at 3 divided mode: adclk = 1/3clk_in sp1 sp2 adclk obp etc. reset bit automatic adjustment taking 40,000adclk period after reset cancellation ? before transfer the reset bit = 0, tg series pulse need to be settled, so address h'00 to h'ef of tg part and h'f4 to h7f7 of cds part should transfer in advance. hd49335 serial data transfer must be stable within the operating power supply voltage range start control of tg and camera dsp a utomatic offset calibration the following describes the above serial data transfer. for details of resistor settings are referred to serial data function table.
hd49335f/hf rev.1.0, feb.25.2004, page 25 of 29 timing specifications of high speed pulse two twh tr twl twl tf 50% 50% t h1dl 90% 10% 90% 10% h2 rg ? h1, h2, rg waveform h1 tf twh tr item h1/h2 rg xv1 to 4 ch1 to 4 xsub/sub_sw min 14 7 ? ? ? typ 20 10 ? ? ? twh max ? ? ? ? ? min 14 ? ? ? ? typ 20 37 ? ? ? twl max ? ? ? ? ? min ? ? ? ? ? typ 8.0 4.0 20 20 20 tr max 14 ? ? ? ? min ? ? ? ? ? typ 8.0 4.0 20 20 20 tf max 14 ? ? ? ? 165 pf 15 pf 15 pf 15 pf 15 pf load capacitance unit ns ns ns ns ns item h1/h2 overlap min 12 typ 20 two power supply specification of h1, h2, rg are 3.0 v to 3.3 v. values are sensor clk = when 18 mhz. max ? unit ns
hd49335f/hf rev.1.0, feb.25.2004, page 26 of 29 notice for use 1. careful handling is necessary to prevent damage due to static electricity. 2. this product has been developed for consumer applications, and should not be used in non-consumer applications. 3. as this ic is sensitive to power line noise, the ground impedance should be kept as small as possible. also, to prevent latchup, a ceramic capacitor of 0.1 f or more an d an electrolytic capacitor of 10 f or more should be inserted between the ground and power supply. 4. common connection of av dd and dv dd should be made off-chip. if av dd and dv dd are isolated by a noise filter, the phase difference should be 0.3 v or less at power-on and 0.1 v or less during operation. 5. if a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure below. hd49335 av ss dv ss av dd dv dd 1 to 4 noise filter a nalog +3.0v hd49335 dv ss av ss dv dd 1 to 4 av dd 100 h 0.01 f noise filter example of noise filte r digital +3.0v 0.01 f 6. connect av ss and dv ss off-chip using a common ground. if there are separate analog system and digital system set grounds, connect to the analog system. 7. when v dd is specified in the data sheet, this indicates av dd and dv dd . 8. no connection (nc) pins are not connected inside the ic , but it is recommended that they be connected to power supply or ground pins or left open to prevent crosstalk in adjacent analog pins. 9. to ensure low thermal resistance of the package, a cu-type lead material is used. as this material is less tolerant of bending than fe-type lead material, careful handling is necessary. 10. the infrared reflow soldering method should be used to mount the chip. note that general heating methods such as solder dipping cannot be used. 11. serial communication should not be performed during the effective video period, since this will result in degraded picture quality. also, use of dedicated ports is recommended for the sck and sdata signals used in the hd49330af. if ports are to be shared with another ic, picture quality should first be thoroughly checked. 12. at power-on, automatic adjustment of the offset voltage generated from pga, adc, etc., must be implemented in accordance with the power-on operating sequence (see page 24). 13. ripple noise of dc/dc converter which generates the voltage of analog part should set under ?50 db with power supply voltage.
hd49335f/hf rev.1.0, feb.25.2004, page 27 of 29 example of recommended external circuit ? slave mode pin 57(test1 = low) 31 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 33 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 24 23 22 21 20 19 18 17 25 26 27 28 29 30 32 50 57 58 59 60 61 62 63 64 56 55 54 53 52 51 49 hd49335 1 1 0.1 47/6 47/6 1000p 100p + xv4 ch1 ch2 ch3 ch4 xsub sub_sw/adck_in sub_pd strob/vgate dv ss 3 av ss adc_in bias vrb vrt vrm hd_in clk_in dv ss 3 dv dd 2 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dv ss 1,2 id xv2 xv1 dv dd 3 dv dd 4 1/4clk_o h2a dv ss 4 dv ss 4 1/2clk_o h1a dv dd 4 dv dd 3 rg reset blkc cds_in av dd blkfb blksh av ss test2 test1 dll_c dv dd 1 mon 41pin_cont cs sdata xv3 vd_in av dd sck 0.1 47/6 0.1 0.1 0.1 0.1 3.0v reset(normally hi) reset(normally hi) to ccd + + 0.1 33k to ccd to ccd id pulse id pulse to v.baff 47 47 47 ? master mode pin 57(test1 = hi) 31 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 33 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 24 23 22 21 20 19 18 17 25 26 27 28 29 30 32 50 57 58 59 60 61 62 63 64 56 55 54 53 52 51 49 hd49335 1 1 0.1 47/6 47/6 1000p 100p + xv4 ch1 ch2 ch3 ch4 xsub sub_sw/adck_in sub_pd strob/vgate dv ss 3 av ss adc_in bias vrb vrt vrm hd_in clk_in dv ss 3 dv dd 2 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dv ss 1,2 id xv2 xv1 dv dd 3 dv dd 4 1/4clk_o h2a dv ss 4 dv ss 4 1/2clk_o h1a dv dd 4 dv dd 3 rg reset blkc cds_in av dd blkfb blksh av ss test2 test1 dll_c dv dd 1 mon 41pin_cont cs sdata unit: r: ? c: f xv3 vd_in av dd sck 0.1 47/6 0.1 0.1 0.1 0.1 ccd signal input ccd signal input 3.0v to ccd + + 0.1 33k ? 61pin = low: pin 41 is strob output pin 39 is sub_sw output 61pin = hi: pin 41 is vgate output pin 39 is hiz ? 61pin = low: pin 41 is strob output pin 39 is sub_sw output 61pin = hi: pin 41 is vgate output pin 39 is hiz to v.baff 47 47 47 ? pin 56 = low: testin mode. please do not use. low hi pin 57 slave mode master mode mode clk, hd, vd input from ssg. hd, vd output specification serial data input serial data input from pulse generator from pulse generator to camera signal processor to camera signal processor to camera signal processor
hd49335f/hf rev.1.0, feb.25.2004, page 28 of 29 ? cds single operating mode pin 56(test2 = low) ? pin 57 is "don't care" in this mode. serial data when cds single operation mode are following resister specifications. (latch timing specification is same as normal mode) 31 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 33 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 24 23 22 21 20 19 18 17 25 26 27 28 29 30 32 50 57 58 59 60 61 62 63 64 56 55 54 53 52 51 49 hd49335 1 1 0.1 47/6 47/6 1000p 100p + pblk obp cp_dm adck sp2 sp1 dv ss 3 av ss adc_in bias vrb vrt vrm dv ss 3 dv dd 2 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dv ss 1,2 dv dd 3 dv dd 4 dv ss 4 dv ss 4 dv dd 4 dv dd 3 reset blkc cds_in av dd blkfb blksh av ss test2 test1 dll_c dv dd 1 mon 41pin_cont cs sdata unit: r: ? c: f av dd sck 0.1 47/6 0.1 0.1 0.1 0.1 3.0v reset(normally hi) + + 0.1 33k ? pin changes are not effective with pin61. adc_in 47 47 47 t int2 fsck tsu cs sck tho t int1 sdata d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d14 d15 d00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 1 1 1 0 0 0 1 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 d01 low low low high low low low high low x high high low low low high high low high low high high high high high resister 4 resister 3 resister 0 resister 1 resister 7 resister 5 resister 6 resister 2 d02 test_i1 (0) d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d14 d15 test_i1 (2) test_i1 (1) pga(0) lsb x slp reset adsel low:cdsin high:adin lopwr stby pga(1) x pga(2) pga(3) pga(4) pga(5) pga(6) pga(7) msb shsw-fsel(3) test_i2 (1) test_i2 (0) output mode(linv) output mode(minv) output mode(test0) sha-fsel(0) sha-fsel(1) shsw-fsel(0) shsw-fsel(1) shsw-fsel(2) mon(0) mon(1) gray_ts(0) gray_ts(2) gray_ts(1) mon(2) h12baff(0) h12baff(1) h12baff(2) h12baff(3) vd latch gray1 gray2 p_sp1(0) p_sp1(1) dll_ck(2) dll_current dll_ck(3) p_sp2(0) p_sp2(1) p_adclk(0) p_adclk(1) p_rg(0) p_rg(1) dll_ck(0) dll_ck(1) dl_sp1(0) dl_sp1(1) dl_adclk(2) cds_test dl_adclk(3) dl_sp1(2) dl_sp1(3) dl_sp2(0) dl_sp2(1) dl_sp2(2) dl_sp2(3) dl_adclk(0) dl_adclk(1) dl_rg_r(0) dl_rg_r(1) dummy cp(0) dummy cp(2) dummy cp(1) dl_rg_r(2) dl_rg_r(3) dl_rg_f(0) dl_rg_f(1) dl_rg_f(2) dl_rg_f(3) dmcg(0) dmcg(1) clamp(0) clamp(1) clamp(2) clamp(3) clamp(4) hgstop-hsel(0) hgstop-hsel(1) hgain-nsel(0) hgain-nsel(1) test ccd signal input serial data input to camera signal processor low: normal high: sleep low: normal high: standby low: normal high: low power low: reset high: normal
hd49335f/hf rev.1.0, feb.25.2004, page 29 of 29 package dimensions package code jedec jeita mass (reference value) tfp-64c ? conforms 0.4 g 0.07 +0.03 -0.06 *dimension including the plating thickness base material dimension 33 48 10.0 12.0 0.2 12.0 0.2 49 64 0.5 0.08 m *0.21 0.05 116 17 32 0.10 1.20 max *0.17 0.05 0.50 0.1 0? ? 8? 1.0 0.19 0.04 1.25 1.0 1.25 0.15 0.04 as of january, 2003 unit: mm
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